1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device using a clock.
2. Description of the Related Art
In general, a semiconductor device operates at a predetermined operation speed in a semiconductor system. This requires the use of a clock which pulses at a predetermined interval which is provided by a control device in the semiconductor system.
A semiconductor device such as a Dynamic Random Access Memory (DRAM) device performs a refresh operation in synchronization with a clock. This specification uses a semiconductor device capable of performing a refresh operation as an example of the related art and also as an embodiment of the present invention.
FIG. 1 is a block diagram illustrating a semiconductor device 100 according to a prior art.
Referring to FIG. 1, the semiconductor device 100 includes a refresh operation portion 110, a normal operation portion 120, and a row control portion 130. The refresh operation portion 110 sequentially generates first to eighth refresh operation control signals REF_RACTV<0:7> during a predetermined refresh period in response to an idle signal IDLE, a refresh source signal AFACT, a clock ICLK and counting codes RAS<0:4>. The normal operation portion 120 sequentially generates first to eighth normal operation control signals ACT_RACTV<0:7> during a predetermined normal period in response to an active signal ACT, a pre-charge signal PCG, and first to eighth bank addresses BA<0:7>. The row control portion 130 generates the idle signal IDLE and first to eighth row active signals RACTV<0:7> in response to the first to eighth refresh operation control signals REF_RACTV<0:7> and the first to eighth normal operation control signals ACT_RACTV<0:7>.
FIG. 2 is a block diagram illustrating the refresh operation portion 110 shown in FIG. 1.
Referring to FIG. 2, the refresh operation portion 110 includes a refresh operation initiation block 111, a refresh operation termination block 113, and a refresh operation control block 115. The refresh operation initiation block 111 sequentially generates first to eighth refresh operation initiation signals FACT<0:7> during a refresh period in response to the refresh source signal AFACT and the idle signal IDLE. The refresh operation termination block 113 sequentially generates first to eighth refresh operation termination signals RE<0:7> in response to the first to eighth refresh operation initiation signals FACT<0:7>, the clock ICLK, and the counting codes RAS<0:4>. The refresh operation control block 115 generates first to eighth refresh operation control signals REF_RACTV<0:7> in response to the first to eighth refresh operation initiation signals FACT<0:7> and the first to eighth refresh operation termination signals RE<0:7>.
FIG. 3 is a block diagram illustrating the refresh operation initiation block 111 shown in FIG. 2.
Referring to FIG. 3, the refresh operation initiation block 111 includes a refresh operation initiation control unit 111_1 and a refresh operation initiation signal generation unit 111_3. The refresh operation initiation control unit 111_1 generates a refresh operation initiation control signal REF, which is enabled during the refresh period in response to the refresh source signal AFACT and the idle signal IDLE. The refresh operation initiation signal generation unit 111_3 generates the first to eighth refresh operation initiation signals FACT<0:7> by sequentially delaying the refresh operation initiation control signal REF. The refresh operation initiation control unit 111_1 enables the refresh operation initiation control signal REF in response to the refresh source signal AFACT and disables the refresh operation initiation control signal REF in response to the idle signal IDLE. For example, the refresh operation initiation control unit 111_1 is an RS latch. The refresh operation initiation signal generation unit 111_3 includes first to seventh unit delayers 111_31A to 111_31G and first to eighth pulse generators 111_33A to 111_33H. The first to seventh unit delayers 111_31A to 111_31G, which are coupled in cascade structure, respectively generate the first to seventh delay signals REF_D0 to REF_D6 by sequentially delaying the refresh operation initiation control signal REF and the delay signal of the previous stage with a predetermined amount of delay. The first to eighth pulse generators 111_33A to 111_33H generate the first to eighth refresh operation initiation signals FACT<0:7> respectively corresponding to the refresh operation initiation control signal REF and the first to seventh delay signals REF_D0 to REF_D6. For example, each of the first to eighth pulse generators 111_33A to 111_33H is a rising edge detector generating a pulse by detecting a rising edge of an input signal.
Referring back to FIG. 2, the refresh operation termination block 113 counts the clock ICLK in response to each enablement of the first to eighth refresh operation initiation signals FACT<0:7>. When each count of the refresh operation termination block 113 reaches a predetermined count number corresponding to the counting codes RAS<0:4>, for example 2 cycles of the clock ICLK, the refresh operation termination block 113 enables each of the first to eighth refresh operation termination signals RE<0:7> in synchronization with the clock ICLK. For example, the refresh operation termination block 113 is a counter.
The refresh operation control block 115 enables the first to eighth refresh operation control signals REF_RACTV<0:7> in response to the first to eighth refresh operation initiation signals FACT<0:7> and disables the first to eighth refresh operation control signals REF_RACTV<0:7> in response to the first to eighth refresh operation termination signals RE<0:7>. For example, the refresh operation control block 115 includes first to eighth RS latches.
FIG. 4 is a block diagram illustrating the normal operation portion 120 shown in FIG. 1.
Referring to FIG. 4, the normal operation portion 120 includes a normal operation initiation block 121, a normal operation termination block 123 and a normal operation control block 125. The normal operation initiation block 121 generates first to eighth normal operation initiation signals ACTP<0:7> in response to the active signal ACT and the first to eighth bank addresses BA<0:7>. The normal operation termination block 123 generates first to eighth normal operation termination signals PCGP<0:7> in response to the pre-charge signal PCG and the first to eighth bank addresses BA<0:7>. The normal operation control block 125 generates the first to eighth normal operation control signals ACT_RACTV<0:7> in response to the first to eighth normal operation initiation signals ACTP<0:7> and the first to eighth normal operation termination signals PCGP<0:7>.
The normal operation initiation block 121 enables one or more of the first to eighth normal operation initiation signals ACTP<0:7> by performing a logic operation on the active signal ACT and the first to eighth bank addresses BA<0:7>.
The normal operation termination block 123 enables one or more of the first to eighth normal operation termination signals PCGP<0:7> by performing the logic operation on the pre-charge signal PCG and the first to eighth bank addresses BA<0:7>.
The normal operation control block 125 enables the first to eighth normal operation control signals ACT_RACTV<0:7> in response to the first to eighth normal operation initiation signals ACTP<0:7> and disables the first to eighth normal operation control signals ACT_RACTV<0:7> in response to the first to eighth normal operation termination signals PCGP<0:7>.
FIG. 5 is a block diagram illustrating the row control portion 130 shown in FIG. 1.
Referring to FIG. 5, the row control portion 130 includes a row active signal generation block 131 and an idle signal generation block 133. The row active signal generation block 131 enables the first to eighth row active signals RACTV<0:7> when the first to eighth refresh operation control signals REF_RACTV<0:7> are enabled, or when the first to eighth normal operation control signals ACT_RACTV<0:7> are enabled. The idle signal generation block 133 enables the idle signal IDLE when the first to eighth row active signals RACTV<0:7> are disabled.
An operation of the semiconductor device 100 is described hereafter with reference to FIG. 6.
FIG. 6 is a timing diagram illustrating a refresh operation of the semiconductor device 100 shown in FIG. 1. FIG. 6 shows the refresh operation as an example of the operation of the semiconductor device 100.
Referring to FIG. 6, the refresh operation initiation block 111 sequentially enables the first to eighth refresh operation initiation signals FACT<0:7> during a refresh operation section in response to the refresh source signal AFACT. The refresh operation initiation block 111 enables each of the first to eighth refresh operation initiation signals FACT<0:7> at an interval of a predetermined amount of delay tPILED.
The refresh operation termination block 113 enables each of the first to eighth refresh operation termination signals RE<0:7> in response to each count of the clock ICLK reaching the predetermined count number corresponding to the counting codes RAS<0:4>, for example 2 cycles of the clock ICLK. As described above, the refresh operation termination block 113 counts the clock ICLK in response to each enablement of the first to eighth refresh operation initiation signals FACT<0:7> until each count of the refresh operation termination block 113 reaches the predetermined count number corresponding to the counting codes RAS<0:4>, for example 2 cycles of the clock ICLK. When each count of the refresh operation termination block 113 reaches the predetermined count number corresponding to the counting codes RAS<0:4>, for example 2 cycles of the clock ICLK, the refresh operation termination block 113 enables each of the first to eighth refresh operation termination signals RE<0:7> in synchronization with the clock ICLK.
The refresh operation control block 115 sequentially generates the first to eighth refresh operation control signals REF_RACTV<0:7> during the refresh period in response to the first to eighth refresh operation initiation signals FACT<0:7> and the first to eighth refresh operation termination signals RE<0:7>. In other words, the refresh operation control block 115 enables the first to eighth refresh operation control signals REF_RACTV<0:7> in response to the first to eighth refresh operation initiation signals FACT<0:7> and disables the first to eighth refresh operation control signals REF_RACTV<0:7> in response to the first to eighth refresh operation termination signals RE<0:7>.
The semiconductor device 100 having such structure described above performs the refresh operation by using the signals in synchronization with the clock, and thus it is easy to control the semiconductor device 100.
However, the following problem exists in the semiconductor device 100 having the structure described above.
FIG. 6 illustrates a case where the predetermined amount of delay tPILED between the first to eighth refresh operation initiation signals FACT<0:7> is longer than a time tCK corresponding to a period of the clock ICLK (tPILED>tCK). Therefore, the refresh operation of the semiconductor device 100 works when the first to eighth refresh operation termination signals RE<0:7> are generated in synchronization with the clock ICLK. However, when the predetermined amount of delay tPILED between the first to eighth refresh operation initiation signals FACT<0:7> is shorter than the time tCK corresponding to the period of the clock ICLK (tPILED<tCK), the following problem may arise. This problem is described below with reference to the drawing FIG. 7.
FIG. 7 a timing diagram illustrating a refresh operation of the semiconductor device 100 shown in FIG. 1.
Referring to FIG. 7, while the first to eighth refresh operation initiation signals FACT<0:7> are delayed with the predetermined amount of delay tPILED and sequentially generated, the first to eighth refresh operation termination signals RE<0:7> are not sequentially and simultaneously generated at the same time, unlike the first to eighth refresh operation initiation signals FACT<0:7>. This is because the first to eighth refresh operation termination signals RE<0:7> are generated in synchronization with the clock ICLK. Accordingly, the semiconductor device 100 has a problem with power noise caused by the disablement of the first to eighth refresh operation control signals REF_RACTV<0:7> occurring at the same time.